1. Field of the Invention
The invention relates to an analog-to-digital converter, and more particularly, relates to a successive approximation register analog-to-digital converter.
2. Description of Related Art
In recent years, as a trend in integrated circuit design, requirements for less power consumption, higher performance and less cost become even more stringent. In design of an analog front-end circuit, one efficient analog-to-digital converter (ADC) is capable of significantly improving overall performance for a system. The ADC is responsible for converting received analog signals into digital signals to be provided to a digital signal processing unit at back-end for operations. Therefore, dynamic range, resolution, accuracy, linearity, sampling speed, power consumption, and input stage characteristic of the ADC all become important parts for influencing overall performance of the system as well as important parameters for evaluating performance of a converter itself.
There is a wide variety of architectures for the existing ADC, such as a pipeline analog-to-digital converter (pipeline ADC) and a successive approximation register analog-to-digital converter (SAR-ADC); both are common architectures in the technical field. Among them, under the same specification requirement, the SAR-ADC is advantageous in having lower power consumption and smaller chip area as compared to the pipeline ADC. Therefore, technical development for a SAR-ADC architecture has gradually being taken seriously by the industry.
The existing SAR-ADC architecture generally includes parts such as a digital-to-analog converter (DAC), a comparison circuit, a SAR logic control circuit, and so forth. Specifically, during operations of an analog-to-digital conversion of the traditional SAR-ADC, the DAC normally uses a reference voltage as a basis for performing sample-and-hold on an analog input signal. Thereafter, a SAR logic control circuit uses a binary search algorithm to control a digital-to-analog conversion of the DAC, so that the DAC may generate a corresponding comparison signal. The comparison signal is related to a voltage difference value between analog voltages corresponding to different logic states and the analog input signal. Subsequently, the comparison circuit may use the reference voltage as a basis for comparing with the comparison signal, such that the SAR logic control circuit is capable of determining a logic state of each of bits of a digital logic signal one by one according to a comparison result of the comparison circuit.
In view of above operations, it can be known that, in order to realize the operations of the analog-to-digital conversion in the existing SAR-ADC architecture, it is required to provide the additional reference voltage as the basis for caparison of a comparator. In addition, for maintaining accuracy of the determination of the comparison circuit, operations of an offset cancellation are generally performed during a period before the analog-to-digital conversion is performed by the SAR-ADC. In such offset cancellation, it is also required to provide one reference voltage as a common-mode voltage for two input terminals of the comparison circuit, so as to cancel a voltage offset between the different input terminals of the comparison circuit.
Furthermore, based on the existing SAR-ADC architecture, the comparator is usually realized by utilizing a comparator composed of one single operation amplifier. Accordingly, when circuits are operated in high frequency, the comparator may cause the SAR-ADC to generate serious noise interference due to required operating current being greater.